Memory Optimization
SRAM budget recovery sprint
Reclaims headroom in on-chip SRAM through section placement, struct packing, and bounded buffers.
Indicative fee: 4 100 000 Ft · informational only
Scope narrative
Memory pressure shows up late—often when a new sensor mode ships. This sprint maps your linker output, static allocations, and runtime peaks, then delivers a staged plan that preserves MISRA-friendly patterns. We stay close to your toolchain so the changes are boring to merge and easy to defend in design reviews.
Included focus areas
- Linker map diff with section-level commentary
- Struct and enum packing review with safety annotations
- Buffer sizing model tied to clinical scenarios you provide
- Optional tooling script to flag regressions in CI
- Walkthrough with your embedded security engineer on secrets handling
- Handoff memo for manufacturing diagnostics teams
Outcomes you can archive
- Documented SRAM recovery with before/after metrics
- Lower risk of late-stage flash repartitioning
- Cleaner collaboration between application and BSP teams
FAQ
Will you touch third-party libraries?
We document upstream constraints first. Changes stay in your wrappers unless the license explicitly allows more.
Can you sign our vendor NDA?
Yes. We use your paper or ours, subject to mutual agreement.
What if we discover a silicon erratum?
We isolate mitigations and document the verification impact. Silicon issues remain with the silicon vendor.
Experience notes
They reframed our SRAM issue as a placement problem, not a mystery. The CI hook caught a regression two sprints later.
Clear diffs, no drama. The walkthrough with security saved us a week of back-and-forth.